Clevo M728T Service Manual download pdf (Page 80)

Schematic Diagrams

B - 6 Cantiga 2/6 - VGA, CRT

B.Schematic Diagrams

Cantiga 2/6 - VGA, CRT

D AC_ RED[1 2 ]

MC H_ CFG 9[9]

GF X _V I D1

C3 9 5

0.01U _16V_X7R_04

Zdiff= 100O? 5%

M_CLK_DDR#3 [11]

D MI_ RXN1 [14 ]

M_CKE0 [10]

M_CKE3 [11]

DMI_TXN1 [14]

D MI_ RXN2 [14 ]

M_CKE1 [10]

C L_PWR OK [12,15,17,26]

LV D S _ L3 P

LV D S - L 2N[1 2 ,27 ]

MCH_C LKR EQ# [18]

M_CLK_DDR0 [10]

SM_ PW RO K

R221 499_1%_04

SM _VR EF

DMI_TXP3 [14]

DAC_RED

R68

10K_1% _04

1.8V

M_CLK_DDR#0 [10]

R 4 9 15 0 _1 % _ 04

3. 3V S

SM_ R EXT

R65 10K_04

1.05VS

PM_ DPR SLP VR[1 5 ,31 ]

LV D S - L 1N[1 2 ,27 ]

MCH_IC H_SYN C# [15]

GF X _V I D2

MCH_C FG11

R32 *10mil_short

D MI_RXP2 [14]

MCH_CFG13[9 ]

R222 80.6_1%_04

MCH_C FG14

D MI_RXP1 [14]

MCH_CFG16[9 ]

M_ODT2 [11]

R64

49 . 9 _1 % _ 04

CL _ VREF

M _C S#0 [10]

LVDS-LC LKP[12 ,2 7 ]

DMI_TXP0 [14]

R58 10K_04

GF X _V I D4

GF X _V I D0

DAC_ D DCAC L K[12 ]

MCH_C FG18

CLK_PCIE_3GPLL# [18]

DMI_TXN2 [14]

D MI_ RXN3 [14 ]

PM_ EXT TS_ EC #

MCH_C FG15

1.05VM_PEG

DMI_TXP2 [14]

MC H_ CFG 7[9]

DAC _ GREEN

R60 *10mil_short

R43 75_04

DAC _ HSYN C[1 2 ]

SM_ RC OM P_V OL

MI SC

DDR CLK/ CONTROL/COMPENSATIONCL KDM I

CFGRSVD

GR AP HI CS V IDME

HDA

U15B

CANTIGA-EB88CTGM

AP2 4

AT2 1

AV2 4

AR 24

AR 21

AU 24

BC 28

AY 28

AY 36

BB3 6

BA1 7

AY 16

AV1 6

AR 13

BC 36

BD 17

AY 17

BF1 5

AY 13

BG 22

BH 21

P2 9

R2 8

P2 5

T2 5

R2 5

T2 8

P2 0

P2 4

C2 5

N2 4

M2 4

E2 1

C2 3

C2 4

N2 1

P2 1

T2 1

R2 0

M2 0

L2 1

H2 1

R2 9

N3 3

P3 2

AT4 0

AT1 1

B38

A38

E41

F41

AE4 1

AE3 7

AE4 7

AH 39

AE4 0

AE3 8

AE4 8

AH 40

AE3 5

AE4 3

AE4 6

AH 42

AD 35

AE4 4

AF4 6

AH 43

AL3 4

AN35

AK34

AM3 5

BG23

BF2 3

BH18

BF1 8

AU 20

AV2 0

AY21

AH9

AH10

AH12

AH13

M3 6

N3 6

R3 3

T3 3

B33

B32

G33

F33

C34

BF2 8

BH 28

T2 0

R3 2

K1 2

AH 37

AH 36

AN 36

AJ 3 5

AH 34

A4 7

BG48

BF4 8

BD48

BC48

BH47

BG47

BE47

BH46

BF4 6

BG45

BH44

BH43

BH6

BH5

BG4

G36

E36

K36

T2 4

H36

B12

E43

F43

BH3

E33

B3 1

N28

BF3

BH2

BG2

BE2

BG1

BF1

BD1

BC1

AV4 2

AR 36

BF1 7

B2 8

B3 0

B2 9

C2 9

A2 8

M28

SA_C K_0

SA_C K_1

SB_C K_0

SA_C K#_0

SA_C K#_1

SB_C K#_0

SA_ C KE_0

SA_ C KE_1

SB_ C KE_0

SB_ C KE_1

SA_C S#_0

SA_C S#_1

SB_C S#_0

SB_C S#_1

SM_ DR AMR ST#

SA_ O DT_0

SA_ O DT_1

SB_ O DT_0

SB_ O DT_1

SM _R CO MP

SM_RCOMP#

CF G _ 18

CF G _ 19

CF G _ 2

CF G _ 0

CF G _ 1

CF G _ 20

CF G _ 3

CF G _ 4

CF G _ 5

CF G _ 6

CF G _ 7

CF G _ 8

CF G _ 9

CF G _ 10

CF G _ 11

CF G _ 12

CF G _ 13

CF G _ 14

CF G _ 15

CF G _ 16

CF G _ 17

PM_ SY NC#

PM_ EXT _TS# _ 0

PM_ EXT _TS# _ 1

PW RO K

RST IN #

DPLL_REF_CLK

D P LL _ R E F _ C LK #

DPLL_R EF_SSCLK

DPLL_REF_SSCLK#

DMI_RXN_0

DMI_RXN_1

DMI_RXN_2

DMI_RXN_3

DM I_R X P_0

DM I_R X P_1

DM I_R X P_2

DM I_R X P_3

DMI_TXN_0

DMI_TXN_1

DMI_TXN_2

DMI_TXN_3

DMI_ TX P_0

DMI_ TX P_1

DMI_ TX P_2

DMI_ TX P_3

RSV D 1 0

RSV D 1 2

RSV D 1 1

RSV D 1 3

RSV D 2 2

RSV D 2 3

RSV D 2 4

RSV D 2 5

PM_ D PRSTP#

SB_C K_1

SB_C K#_1

RSV D 2 0

RSV D 5

RSV D 6

RSV D 7

RSV D 8

RSV D 1

RSV D 2

RSV D 3

RSV D 4

GFX_VID _0

GFX_VID _1

GFX_VID _2

GFX_VID _3

GFX_VR_EN

SM_ RC OMP_ VO H

SM _R CO MP_ VOL

THER MTRIP#

DPR SL PVR

RSV D 9

CL_CLK

CL _ DATA

CL_PWROK

CL_RST#

CL _V REF

NC _2 6

NC _1

NC _2

NC _3

NC _4

NC _5

NC _6

NC _7

NC _8

NC _9

NC _1 0

NC _1 1

NC _1 2

NC _1 3

NC _1 4

NC _1 5

SDVO _ CTRL CLK

SDVO _CTRLDATA

C LKR EQ#

RSV D 1 4

ICH_SYNC#

TSATN#

PEG_ C LK#

PEG_CLK

NC _1 6

GFX_VID _4

RSV D 1 5

DDPC _CTRLCLK

NC _1 7

NC _1 8

NC _1 9

NC _2 0

NC _2 1

NC _2 2

NC _2 3

NC _2 4

NC _2 5

SM _V REF

SM_ PW R OK

SM_ R EXT

RSV D 1 7

HD A_ BCL K

HD A_ RST#

HD A_ SDI

HD A_ SDO

HD A_ SYNC

DDPC _ CTRL DAT A

RSV D 1 6

MCH_CFG10[9 ]

M CH_BSEL0[4 ]

96MHz

LV D S - L 2P[1 2 ,27 ]

CLK_DREF [18]

MC H_ CFG 6[9]

DMI_TXN0 [14]

R232

1K_1%_04

R2 3 6

2.37K_1%_04

C1 3 1

0.1U_10V_X7R _04

LVDS-LCLKN[1 2 ,27 ]

SM_ RC OMP#

R63

1K_1% _04

M_ODT0 [10]

100MHz

LV D S - L 1P[1 2 ,27 ]

LV D S - L 0P[1 2 ,27 ]

M_CLK_DDR2 [11]

C392

2.2U_6.3V _06

DAC_BLUE[1 2]

H_DPRSTP#[2 ,1 3,3 1 ]

MCH_C FG17

R44 75_04

3.3VS[8..16,18..27,31]

SM_ RC OMP

R69

10K_1% _04

ENAVD D[12 ]

MCH_CFG12[9 ]

100MHz

G M_BLON[1 2 ]

LV D S - L 0N[1 2 ,27 ]

MC H_ CL KRE Q#

MCH_C FG3

LV D S _ L3 N

M_CLK_DDR3 [11]

1. 8 V

R 4 7 15 0 _1 % _ 04

SM_RC OMP_VO H

SM _RCO MP_VOL

PM_ EXT TS_EC #

PM_ EXT TS_ D DR#

M CH_ CLKR EQ#

R59 10K_04

M CH_BSEL2[4 ]

C L K _P C IE_ 3G PL L [1 8]

R61 *10m il_short

DMI_TXN3 [14]

MCH_CFG19[9 ]

C L_DA TA0 [15]

MC H_ CFG 5[9]

R230

3.01K_1%_04

C L K_D REFSS# [18 ]

P L T_ R S T#[14 ,1 9]

MCH_C FG8

DMI_TXP1 [14]

M_CLK_DDR#2 [11]

GF X _V R E N

R30 100_04

M _C S#2 [11]

M _C S#1 [10]

M_C KE2 [11]

PM_ T HR MTRIP #[2, 13,2 8]

1 . 05 V M _P E G[8 ]

GF X _V I D3

M_ODT1 [10]

M_CLK_DDR#1 [10]

MCH_C FG4

1.05VS[2..4,7,8,13,16,29]

D MI_ RXN0 [14 ]

DAC_GREEN

P_ DD C_ CL K[12 ,2 7 ]

C399

2.2U_6.3V _06

C1 1 8

0 . 1U _1 0 V _ X7 R _0 4

D MI_RXP3 [14]

M_CLK_DDR1 [10]

PM_ EXT TS_D DR#

P_ DD C_DA T A[12 ,27 ]

PM_ SYN C#[1 5]

R5 2 1 K_ 1% _ 0 4

R 3 61 5 6 _0 4

CLK_DREF# [18]

DAC_BLUE

C3 9 8

0.01U _16V_X7R_04

12mils

R 4 8 15 0 _1 % _ 04

C L K_D REFSS [1 8]

R53 30.1_1% _04

R226 80.6_1%_04

DAC_DDCADATA[12 ]

1. 8 V

1.8V[7 ,8, 10 ,1 1,3 0 ]

R62

5 1 1_ 1 % _0 4

C L_CLK0 [15]

D MI_RXP0 [14]

R55 *10mil_short

12mils

DAC _ GREE N[1 2 ]

R 2 16 * 1 0m i l _s h or t

CL_VREF

SM _RCO MP_VOH

PM_ EXT TS_DD R#[10 ,1 1]

R42 75_04

DAC _ RED

SM_ PW R OK

1. 0 5 V S

R54 30.1_1% _04

LVDS

PCI-EXPRESS GRAPHICS

TV VGA

U1 5C

CANT IG A-EB8 8C TG M

T3 7

T3 6

H4 4

J4 6

L4 4

L4 0

N4 1

P48

N4 4

T4 3

U4 3

Y4 3

Y4 8

Y3 6

AA43

AD37

AC47

AD39

H4 3

J4 4

L4 3

L4 1

N4 0

P47

N4 3

T4 2

U4 2

Y4 2

W47

Y3 7

AA42

AD36

AC48

AD40

J4 1

Y4 0

M4 0

M4 2

R4 8

N3 8

T4 0

U3 7

U4 0

M4 6

AA46

AA37

AA40

AD43

AC46

M4 7

J4 2

L4 6

M4 8

M3 9

M4 3

R4 7

N3 7

T3 9

U3 6

U3 9

Y3 9

Y4 6

AA36

AA39

AD42

AD46

M32

M33

K33

J33

M29

C44

B43

E37

E38

C41

C40

H47

E46

G40

D45

F40

B37

A37

A41

H38

G37

G38

F37

G32

F25

H25

K25

H24

E28

H32

J32

G28

J29

E29

J28

G29

L29

H48

B42

L32

C31

E32

A40

B40

J37

K37

PEG_ CO MPI

PE G_ COM PO

PEG_ RX#_ 0

PEG_ RX#_ 1

PEG_ RX#_ 2

PEG_ RX#_ 3

PEG_ RX#_ 4

PEG_ RX#_ 5

PEG_ RX#_ 6

PEG_ RX#_ 7

PEG_ RX#_ 8

PEG_ RX#_ 9

PEG _R X# _ 1 0

PEG _R X# _ 1 1

PEG _R X# _ 1 2

PEG _R X# _ 1 3

PEG _R X# _ 1 4

PEG _R X# _ 1 5

PEG_RX_0

PEG_RX_1

PEG_RX_2

PEG_RX_3

PEG_RX_4

PEG_RX_5

PEG_RX_6

PEG_RX_7

PEG_RX_8

PEG_RX_9

PEG_ RX_1 0

PEG_ RX_1 1

PEG_ RX_1 2

PEG_ RX_1 3

PEG_ RX_1 4

PEG_ RX_1 5

PEG_TX# _ 0

PEG_TX#_10

PEG_TX# _ 3

PEG_TX# _ 4

PEG_TX# _ 5

PEG_TX# _ 6

PEG_TX# _ 7

PEG_TX# _ 8

PEG_TX# _ 9

PEG_TX# _ 1

PEG_TX#_11

PEG_TX#_12

PEG_TX#_13

PEG_TX#_14

PEG_TX#_15

PEG_TX# _ 2

PEG _TX_0

PEG _TX_1

PEG _TX_2

PEG _TX_3

PEG _TX_4

PEG _TX_5

PEG _TX_6

PEG _TX_7

PEG _TX_8

PEG _TX_9

PEG_TX_ 1 0

PEG_TX_ 1 1

PEG_TX_ 1 2

PEG_TX_ 1 3

PEG_TX_ 1 4

PEG_TX_ 1 5

L_CTRL_CLK

L_CTRL_DATA

L_DD C_CLK

L_DD C_DATA

L_VDD _EN

LVD S_IBG

LVD S_VBG

LVDS_VREFH

LVDS_VREFL

LVDSA_CLK#

LVDSA_CLK

LVDSA_DATA#_0

LVDSA_DATA#_1

LVDSA_DATA#_2

LVDSA_DATA_1

LVDSA_DATA_2

LVDSB_CLK#

LVDSB_CLK

LVDSB_DATA#_0

LVDSB_DATA#_1

LVDSB_DATA#_2

LVDSB_DATA_1

LVDSB_DATA_2

L_BKLT_EN

TVA_DAC

TVB_DAC

TVC_DAC

TV_RTN

CRT_BLUE

C RT _ DDC _ CL K

C RT _ DDC _ DATA

CRT_GREEN

CRT_HSYNC

CRT_TVO_IREF

CRT_RED

CRT_IRTN

C RT_ VSYN C

LVDSA_DATA_0

LVDSB_DATA_0

L_BKLT_CTR L

TV_DC ONS EL_0

TV_DC ONS EL_1

LVDSA_DATA#_3

LVDSA_DATA_3

LVDSB_DATA#_3

LVDSB_DATA_3

MCH_CFG20[9 ]

M _C S#3 [11]

R229

1K_1%_04

DELAY_PWRGD[1 7,3 1 ]

M CH_BSEL1[4 ]

M_ODT3 [11]

DAC _VSY NC[12 ]

C L_RS T#0 [15]

SM_ REXT

Sheet 5 of 40

Cantiga 2/6 -

VGA, CRT

1 2 ... 75 76 77 78 79 80 81 82 83 84 85 ... 115 116

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Clevo M728T Service Manual Page 80

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